1. Field of the Invention
This invention relates generally to multi-processor computer systems. More specifically, it relates to the use of address and control lines of a bus connecting multiple processors and special purpose Very Large Scale Integration (VLSI) gate arrays.
2. Background Information
Many computer systems today are composed of multiple processing units in order to increase their processing power. These programmable processors often must interact with hardwired logic such as VLSI gate arrays. Some functions of complex computer systems are performed by such hardware because of the increased speed capabilities this hardware provides. However, other functions may be better implemented in software or firmware because of the flexibility software or firmware provides. In a large computer system such as the Extended Processing Complex (XPC), a file cache system designed to operate in conjunction with a 2200 Series computer system, both of which are available from Unisys Corporation, some capabilities of embedded subsystems are implemented in a combination of hardware and software/firmware. These subsystems performed required functions as components of the larger system. These subsystems combine the increased speed of hardware implementations with the flexible nature of programming to efficiently satisfy subsystem requirements.
The processors and VLSI gate arrays present in these subsystems communicate with each other over a bus. A bus is an electronic pathway in a digital computer that provides a communication path for transferring data signal and other signals between a processor and a peripheral device. A bus contains one signal line for each bit needed to specify the address of a device or location in memory, plus additional signal lines that distinguish among the various data transfer operations to be performed. A bus can transmit data in either direction between any two components connected to it. Without a bus, separate lines would be needed for all possible connections between the components. The use of a bus avoids this complexity.
However, the use of a bus has its limitations. The number of storage locations resident on a device connected to the bus that are directly addressable by a processor on the bus is limited to 2** N, where N is the number of lines available for carrying address information. In many of today's complicated VLSI gate array designs, such as those used in the XPC, the number of pins available for address lines is limited, but the size of memory desired to be directly accessed is growing. Thus, if a processor needs to access more storage locations than are possible because of pin out concerns, there is a problem. A mechanism is needed to enlarge the address space of the bus without adding more address lines.
One approach to this problem is to use based addressing rather than direct addressing. In based addressing, the processor writes data specifying a base address into a base register on the VLSI gate array. Subsequent memory references to that VLSI gate array are interpreted as being relative to the base address. This method increases the number of storage locations that are accessible by the processor without increasing the number of address lines. However, there is an increased cost in bus transfers because of the need to load the base register frequently. To reference a given storage location, two bus accesses are necessary--one to load the base register and another to specify the offset address. The use of this method in some situations incurs a substantial performance penalty. A more efficient method is needed.
In addition, increased performance in accessing single bit flags called designators located on the gate arrays is needed. A typical method of performing a set or clear operation on a designator includes reading the status location of the designator from the gate array to the processor, updating the status, and writing the status from the processor back into the designator on the gate array. The typical method requires two bus accesses. Similarly, the typical method of performing a test operation on a designator includes reading the status of the designator, shifting and masking the data to isolate the designator status, and testing the flag. Clearly, performance would be improved if the set, clear, and test functions could be accomplished in one bus access.